The invention relates to an electronic circuit in which selection means select a transistor from a group of 2.sup.n multi-emitter transistors each having n emitters under the control of an input signal and make it conductive, of which emitters a selection is connected to n data lines, which data lines further are each connected on the one hand to a current source and on the other hand to an output circuit for generating at the output of the output circuit a binary output signal belonging to a given input signal.
Such a circuit arrangement is known from British GB.PS No. 1,547,918, in which a completely parallel operating analog-to-digital converter is described. In this a-d converter the data on the data lines are compared with a reference voltage by an output circuit to establish whether the data lines carry a logic high or logic low signal. Such a circuit arrangement usually has a small logic stroke (voltage difference between the logic high and low signal) and as a result of this also has a low interference margin. Increasing the logic stroke usually is not possible because only a small voltage range is available in the bipolar very rapidly operating logic often used for this type of circuit arrangements.